Makefile: dependencies and objectives with the same name, varying the route

I'm trying to process files using the GNU Make tool. The goal is to generate files with the same name , but in different routes .

When this decides to work, I will use it as a template to apply a word processor , and be able to perform various actions according to the variables that happen to it. A preprocessed in the style C / C ++, but on files .js .

At the moment, I am dealing with a minimum of routes and files. Later, I will add more.

The hierarchy of routes and files is:

  

+--Makefile
+--src/
| +--main.js
| +--cdump.js
+--build/

The Makefile starts like this:

MAINORG:=$(wildcard src/*.js)
MAINDST:=$(subst src/,build/,$(MAINORG))
MAINFIL:=$(notdir $(MAINORG))

That correctly assigns the variables (checked):

MAINORG -> src/cdump.js src/main.js
MAINDST -> build/cdump.js build/main.js
MAINFIL -> cdump.js main.js

Now, the problem is coming. I try to generate a rule as indicated in Syntax of Static Pattern Rules During the tests, I just show the objective and the requirement :

all: $(MAINFIL)

$(MAINFIL): build/%.js: src/%.js
  @echo $< , $@

Which gives me this pretty exit:

  

Makefile: 14: the target 'cdump.js' does not match the goal pattern

     

Makefile: 14: the target 'main.js' does not match the target pattern

     

, cdump.js

     

, main.js

For trying, I changed the rule, staying like this:

$(MAINFIL): %.js: %.js
  @echo $< , $@

Which alters slightly the output:

  

make: The circular dependency cdump.js < - cdump.js is removed.

     

, cdump.js

     

make: The circular dependency main.js