Error "Output-enabled / tristated signal" in VHDL

I am doing a VHDL code for a GAL and when compiling the whole project (TOP LEVEL), I get this error:

topld:  and.vhd:  (E476) Output-enabled/tristated signal 'x_3' must be an OUT or INOUT port.
topld:  and.vhd:  (E476) Output-enabled/tristated signal 'x_2' must be an OUT or INOUT port.
topld:  and.vhd:  (E476) Output-enabled/tristated signal 'x_1' must be an OUT or INOUT port.
topld:  and.vhd:  (E476) Output-enabled/tristated signal 'x_0' must be an OUT or INOUT port.
topld:  sumador.vhd:  (E476) Output-enabled/tristated signal 'y_0' must be an OUT or INOUT port.
topld:  sumador.vhd:  (E476) Output-enabled/tristated signal 'y_1' must be an OUT or INOUT port.
topld:  sumador.vhd:  (E476) Output-enabled/tristated signal 'y_2' must be an OUT or INOUT port.
topld:  sumador.vhd:  (E476) Output-enabled/tristated signal 'y_3' must be an OUT or INOUT port.

My code is as follows:

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY ALU IS
    PORT(
        Cout    : OUT STD_LOGIC;
        Cin     : IN STD_LOGIC;
        A, B    : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        Z       : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        F       : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
    );
END ALU;

ARCHITECTURE BEHAVIORAL OF ALU IS
    COMPONENT CompAndOr PORT(
        aa, bb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        S    : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        Func : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
    );END COMPONENT;

    COMPONENT SumRes PORT(
        Cin  : IN STD_LOGIC;
        Cout : OUT STD_LOGIC;
        aa, bb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        S    : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        Func : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
    );END COMPONENT;

    COMPONENT mux PORT(
             aa     : IN std_logic_vector(3 DOWNTO 0); 
             bb     : IN std_logic_vector(3 DOWNTO 0); 
             sel    : IN std_logic_vector(1 DOWNTO 0); 
             salida : OUT std_logic_vector(3 DOWNTO 0)
    );END COMPONENT;

    SIGNAL X, Y : STD_LOGIC_VECTOR(3 DOWNTO 0);

    BEGIN
        U1: CompAndOr PORT MAP (A,B,X,F);
        U2: SumRes PORT MAP (Cin,Cout,A,B,Y,F);
        U3: mux PORT MAP (X,Y,F,Z);

END BEHAVIORAL;

The X and Y signals are for the results of the operations within the entities, and I use them so that with the multiplexer only the desired operation comes out